1. Field of the Invention
The present invention relates to a semiconductor memory device, more specifically to a semiconductor memory device for reading memorized data by setting a voltage of a bit line to a predetermined voltage.
2. Description of the Related Art
In a memory cell array constituted in a conventional manner, it is necessary to pre-charge a voltage of a bit line selected in accordance with an inputted address to a predetermined voltage when data in the memory cell is read. In addition, it is necessary to reset the voltage of the bit line to an initial voltage after the data in the memory cell is judged with a sense amplifier. In order to do treatment described above, it is further necessary to wait for a predetermined length of time (in other words, pre-charge the voltage of the bit line) until the data in the memory cell is decided with the sense amplifier after the address is inputted, and also to wait for a predetermined length of time until the data in the next memory cell is read after the data in the current memory cell is decided with the sense amplifier (in other words, reset the voltage of the bit line after reading the data to the initial voltage). Further, it is necessary to wait for a predetermined length of time (in other words, pre-charge the voltage of the bit line) even if it is not after the address is inputted but, for example, it is a reading sequence like pre-charging the voltage of the bit line due to a falling edge of a clock signal. Because of the reason described above, it is not possible to randomly read the data at a high speed.
The problem is generated regardless of the constitution and format of the memory cell. A similar problem is also generated in memory cells in which it is necessary to set the voltage of the bit line before and after the reading operation (including NAND type, AND type, Pch type, Depression type, resistance-variable nonvolatile memory (RRAM) and capacitor) other than an NOR memory cell and a VGA memory cell.
The constitution recited in No. 2003-529880 of the Japanese Patent Applications Laid-Open was proposed in order to solve the problem. According to the cited document, the memory array comprises at least two banks provided with a sense amplifier independently operating, wherein data is alternately read from the respective banks. Accordingly, the bit-line voltage of the memory cell in one of the banks can be reset and pre-charged while the data is being read from the memory cell in the other bank. As a result, it becomes unnecessary to wait until the voltage of the bit line is set before the data can be read from the next memory cell, which enables to read at high speed.
The foregoing constitution is effective when the data is serially read, however, after the data in the memory cell in one of the banks is read, it is necessary to read the data from the memory cell in the other bank. Due to the disadvantage, it is still not possible to start to read the data in the next memory cell until the pre-charge and reset of the bit-line voltage are completed in the case where the data in the memory cells in the same bank is randomly read in succession, in particular, in the case where the data in the memory cells present on the same bit line in the same bank. As described, even in the conventional constitution which was improved, it still requires the time for setting the bit-line voltage when the data is read from the memory cell, thereby it is difficult to randomly read the data at a high speed.